Real-Time Embedded Systems

Real-time embedded systems research in the Memory & Storage Architecture Lab. has focused on the interaction between real-time embedded computing and modern architectures. We have proposed a new approach called the extended timing schema approach to enable timing analysis of modern architectural features such as cache memory, pipelined execution (including superscalar execution), and prefetching. We have also studied the impact of modern architectural features (notably cache memories) on the schedulability analysis. For this purpose, we have extended the classical response time equation to incorporate the effects of cache memory. The extension involves data-flow analysis over tasks' code and integer linear programming to bound additional cache misses due to task preemptions.

Selected Publications

  1. Sheayun Lee, Insik Shin, Woonseok Kim, Insup Lee, and Sang Lyul Min, "A Design Framework for Real-Time Embedded Systems with Code Size and Energy Constraints," ACM Transactions on Embedded Computing Systems, vol. 7, no. 2, Feb. 2008.
  2. Sheayun Lee, Jaejin Lee, Chang Yun Park, and Sang Lyul Min, "Selective Code Transformation for Dual Instruction Set Processors," ACM Transactions on Embedded Computing Systems, vol. 6 no. 2, May 2007.
  3. Kanghee Kim, Jose Luis Diaz, Lucia Lo Bello, Jose Maria Lopez, Chang-Gun Lee, Sang Lyul Min, "An Exact Stochastic Analysis of Priority-Driven Periodic Real-Time Systems and Its Approximations," IEEE Transactions on Computers, vol. 54, no. 11, pp. 1460-1466, Nov. 2005.
  4. Chang-Gun Lee, Kwangpo Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, and Chong Sang Kim, "Bounding Cache-Related Preemption Delay for Real-Time Systems," IEEE Transactions on Software Engineering, vol. 27, no. 9, pp. 805-826, Sep. 2001.
  5. Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, and Chong Sang Kim, "Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling," IEEE Transactions on Computers, vol. 47, no. 6, pp. 700-713, Jun. 1998.
  6. Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, and Chong Sang Kim, "An Accurate Worst Case Timing Analysis for RISC Processors," IEEE Transactions on Software Engineering, vol. 21, no. 7, pp. 593-604, Jul. 1995.